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L6384E
High-voltage half bridge driver
Features

High voltage rail up to 600V dV/dt immunity 50V/nsec in full temperature range Driver current capability: - 400mA source, - 650mA sink Switching times 50/30 nsec rise/fall with 1nF load CMOS/TTL Schmitt trigger inputs with hysteresis and pull down Shut down input Dead time setting Under voltage lock out Integrated bootstrap diode Clamping on VCC SO-8/DIP-8 packages Block diagram
H.V. VCC 2 8 BOOTSTRAP DRIVER UV DETECTION R IN 1 VCC Idt DT/SD 3 Vthi
D97IN518A
DIP-8
SO-8
Description
The L6384E is an high-voltage device, manufactured with the BCD"OFF-LINE" technology. It has an Half - Bridge Driver structure that enables to drive N-channel Power MOS or IGBT. The High Side (Floating) Section is enabled to work with voltage Rail up to 600V. The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices. Matched delays between Low and High Side Section simplify high frequency operation. Dead time setting can be readily accomplished by means of an external resistor.

Figure 1.
VBOOT
HVG DRIVER S 7
CBOOT HVG
LOGIC LEVEL SHIFTER DEAD TIME VCC
OUT 6
LOAD
5 LVG DRIVER
LVG
4
GND
October 2007
Rev 1
1/17
www.st.com 17
Contents
L6384E
Contents
1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 1.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 3
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 3.2 3.3 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 6 7 8
Typical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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L6384E
Electrical data
1
1.1
Electrical data
Absolute maximum ratings
Table 1.
Symbol Vout Vcc Is Vboot Vhvg Vlvg Vi Vsd dVout/dt Ptot TJ Ts Output voltage Supply voltage Supply current
(1) (1)
Absolute maximum ratings
Parameter Value -3 to Vboot -18 - 0.3 to 14.6 25 -1 to 618 -1 to Vboot -0.3 to Vcc +0.3 -0.3 to Vcc +0.3 -0.3 to Vcc +0.3 50 750 150 -50 to 150 Unit V V mA V V V V V V/ns mW C C
Floating supply voltage High side gate output voltage Low side gate output voltage Logic input voltage Shut down/dead time voltage Allowed output slew rate Total power dissipation (Tj = 85 C) Junction temperature Storage temperature
1. The device has an internal Clamping Zener between GND and the Vcc pin, It must not be supplied by a Low Impedence Voltage Source.
Note:
ESD immunity for pins 6, 7 and 8 is guaranteed up to 900 V (Human Body Model)
1.2
Thermal data
Table 2.
Symbol Rth(JA)
Thermal data
Parameter Thermal Resistance Junction to ambient SO-8 150 DIP-8 100 Unit C/W
3/17
Electrical data
L6384E
1.3
Recommended operating conditions
Table 3.
Symbol Vout VBS
(2)
Recommended operating conditions
Pin 6 8 Parameter Output Voltage Floating Supply Voltage Switching Frequency 2 Supply Voltage Junction Temperature -45 HVG,LVG load CL = 1nF Test condition Min
(1) (1)
Typ
Max 580 17 400 Vclamp 125
Unit V V kHz V C
fsw Vcc
Tj
1. If the condition Vboot - Vout < 18V is guaranteed, Vout can range from -3 to 580V. 2. VBS = Vboot - Vout
4/17
L6384E
Pin connection
2
Pin connection
Figure 2. Pin connection (Top view)
IN VCC DT/SD GND 1 2 3 4
D97IN519
8 7 6 5
VBOOT HVG VOUT LVG
Table 4.
N 1 2
Pin description
Pin IN Vcc Type I Function Logic Input: it is in phase with HVG and in opposition of phase with LVG. It is compatible to VCC voltage. [Vil Max = 1.5V, Vih Min = 3.6V] Supply input voltage: there is an internal clamp [Typ. 15.6V] High impedance pin with two functionalities. When pulled lower than Vdt [Typ. 0.5V] the device is shut down. A voltage higher than Vdt sets the dead time between high side gate driver and low side gate driver. The dead time value can be set forcing a certain voltage level on the pin or connecting a resistor between pin 3 and ground. Care must be taken to avoid below threshold spikes on pin 3 that can cause undesired shut down of the IC. For this reason the connection of the components between pin 3 and ground has to be as short as possible. This pin can not be left floating for the same reason. The pin has not be pulled through a low impedance to VCC, because of the drop on the current source that feeds Rdt. The operative range is: Vdt....270K Idt, that allows a dt range of 0.4 - 3.1s. Ground Low Side Driver Output: the output stage can deliver 400mA source and 650mA sink [Typ. Values]. The circuit guarantees 0.3V max on the pin (@ Isink = 10mA) with VCC > 3V and lower than the turn on threshold. This allows to omit the bleeder resistor connected between the gate and the source of the external mosfet normally used to hold the pin low; the gate driver ensures low impedance also in SD conditions. High Side Driver Floating Reference: layout care has to be taken to avoid below ground spikes on this pin. High Side Driver Output: the output stage can deliver 400mA source and 650mA sink [Typ. Values]. The circuit gurantees 0.3V max between this pin and Vout (@ Isink = 10mA) with VCC > 3V and lower than the turn on threshold. This allows to omit the bleeder resistor connected between the gate and the source of the external mosfet normally used to hold the pin low; the gate driver ensures low impedance also in SD conditions. Bootstrap Supply Voltage: it is the high side driver floating supply. The bootstrap capacitor connected between this pin and pin 6 can be fed by an internal structure named "bootstrap driver" (a patented structure). This structure can replace the external bootstrap diode.
3
DT/SD
I
4
GND
5
LVG
O
6
Vout
O
7
HVG
O
8
Vboot
5/17
Electrical characteristics
L6384E
3
3.1
Electrical characteristics
AC operation
Table 5.
Symbol ton tonsd
AC operation electrical characteristcs (VCC = 14.4V; TJ = 25C)
Pin Parameter Test condition Vout = 0V Rdt= 47k Min Typ 200+ dt 220 Vout = 0V Rdt = 47k 250 200 170 50 30 280 300 250 200 Max Unit ns ns ns ns ns ns ns
1 vs High/low side driver turn-on 5,7 propagation delay 3 vs Shut down input propagation 5,7 delay 1 vs High/low side driver turn-off 5,7 propagation delay 5,7 5,7 Rise time Fall time
toff
Vout = 0V Rdt = 146k Vout = 0V Rdt = 270k
tr tf
CL = 1000pF CL = 1000pF
3.2
DC operation
Table 6.
Symbol
DC operation electrical characteristcs (VCC = 14.4V; TJ = 25C)
Pin Parameter Test condition Min Typ Max Unit
Supply voltage section Vclamp Vccth1 Vccth2 Vcchys 2 Iqccu Iqcc 2 2 Supply voltage clamping VCC UV turn on threshold VCC UV turn off threshold VCC UV Hysteresis Undervoltage quiescent supply current Quiescent current Vcc 11V Vin = 0 Is = 5mA 14.6 11.5 9.5 15.6 12 10 2 150 380 500 16.6 12.5 10.5 V V V V A A
Bootstrapped supply voltage section Vboot IQBS ILK Rdson 8 Bootstrap supply voltage Quiescent current High voltage leakage current Bootstrap driver on resistance (1) IN = HIGH Vhvg = Vout = Vboot = 600V Vcc 12.5V; IN = LOW 125 17 200 10 V A A
6/17
L6384E Table 6.
Symbol
Electrical characteristics DC operation electrical characteristcs (continued)(VCC = 14.4V; TJ = 25C)
Pin Parameter Test condition Min Typ Max Unit
High/Low side driver Iso Isi Logic inputs Vil Vih Iih Iil Iref dt Vdt 3 1,3 Low level logic threshold voltage High level logic threshold voltage High level logic input current VIN = 15V Low level logic input current Dead time setting current Rdt = 47k Rdt = 146k Rdt = 270k 0.4 VIN = 0V 28 0.5 1.5 2.7 0.5 3.6 50 70 1 1.5 V V A A A s s s V Source short circuit current 5,7 Sink short circuit current VIN = Vih (tp < 10s) VIN = Vil (tp < 10s) 300 500 400 650 mA mA
3 vs Dead time setting range (2) 5,7 3 Shutdown threshold
3.1
1. RDS(on) is tested in the following way:
( V CC - V CBOOT1 ) - ( V CC - V CBOOT2 ) R DSON = -----------------------------------------------------------------------------------------------------I 1 ( V CC ,V CBOOT1 ) - I 2 ( V CC ,V CBOOT2 )
where I1 is pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2 2. Pin 3 is a high impedence pin. Therefore dt can be set also forcing a certain voltage V3 on this pin. The dead time is the same obtained with a Rdt if it is: Rdt x Iref = V3.
3.3
Timing diagram
Figure 3. Input/output timing diagram
IN SD
HVG LVG
D99IN1017
7/17
Bootstrap driver
L6384E
4
Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 4 a). In the L6384E a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in Figure 4 b. An internal charge pump (Figure 4 b) provides the DMOS driving voltage. The diode connected in series to the DMOS has been added to avoid undesirable turn on of it.
4.1
CBOOT selection and charging
To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge:
Q gate C EXT = -------------V gate
The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be:
CBOOT>>>CEXT
e.g.: if Qgate is 30nC and Vgate is 10V, CEXT is 3nF. With CBOOT = 100nF the drop would be 300mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage losses. e.g.: HVG steady state consumption is lower than 200A, so if HVG TON is 5ms, CBOOT has to supply 1C to CEXT. This charge on a 1F capacitor means a voltage drop of 1V. The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 125 ). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS:
Q gate V drop = I ch arg e R dson V drop = ------------------ R dson T ch arg e
where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor.
8/17
L6384E
Bootstrap driver For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about 1V, if the Tcharge is 5s. In fact:
30nC V drop = -------------- 125 0.8V 5s
Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn't allow a sufficient charging time, an external diode can be used. Figure 4. Bootstrap driver
DBOOT
VS
VBOOT H.V. HVG
VS
VBOOT H.V. HVG
CBOOT VOUT TO LOAD
CBOOT VOUT TO LOAD
LVG
LVG
a
b
D99IN1067
9/17
Typical characteristic
L6384E
5
Typical characteristic
Figure 5.
time (nsec) 250 200 Tr 150 Tf 100 50 0
Typical rise and fall times vs load capacitance
D99IN1015
Figure 6.
Iq (A) 104
Quiescent current vs supply voltage
D99IN1016
103
102
10
0 1 2 3 4 5 C (nF) For both high and low side buffers @25C Tamb
0
2
4
6
8
10
12
14
VS(V)
Figure 7.
Dead time vs resistance
Figure 8.
Driver propagation delay vs temperature
400
3.5 3.0 2.5 dt (s) 2.0 Typ. 1.5 1.0 0.5 0.0 50 100 150 200 Rdt (k) 250 300 @ Vcc = 14.4V
@ Vcc = 14.4V 300 Ton,Toff (ns) Typ. 200 Typ. Typ. @ Rdt = 270kOhm @ Rdt = 146kOhm 0 -45 -25 0 25 50 Tj (C) 75 100 125 @ Rdt = 47kOhm
100
Figure 9.
Dead time vs temperature
Figure 10. Shutdown threshold vs temperature
1
3 2.5 2 dt (s) 1.5 Typ. 1 0.5 Typ. 0 -45 -25 0 25 50 Tj (C) 75 100 125 R=47K R=146K Typ. R=270K
0.8 @ Vcc = 14.4V 0.6 Vdt (V) 0.4 0.2 0 -45 -25 0 25 50 75 100 125 Tj (C) Typ.
@ Vcc = 14.4V
10/17
L6384E
Typical characteristic
Figure 11. Vcc UV turn On vs temperature
15 14
Figure 12. Output source current vs temperature
1000 800 Current (mA)
@ Vcc = 14.4V
600
Typ.
Vccth1 (V)
13 12 11 10 -45 -25 0 25 50 Tj (C) 75 100 125 Typ.
400 200 0 -45
-25
0
25 50 Tj (C)
75
100 125
Figure 13. Vcc UV turn Off vs temperature
13 12 Vccth2 (V) 11 10 9 8 -45 -25 0 25 50 Tj (C) 75 100 125 Typ.
Figure 14. Output sink current vs temperature
1000
@ Vcc = 14.4V
800 Current (mA) 600 400 200 0 -45 -25 0 25 50 Tj (C) 75 100 125
Typ.
11/17
Package mechanical data
L6384E
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
12/17
L6384E
Package mechanical data Figure 15. DIP-8 mechanical data and package dimensions
mm DIM. MIN. A a1 B b b1 D E e e3 e4 F I L Z 3.18 7.95 2.54 7.62 7.62 6.6 5.08 3.81 1.52 0.125 0.51 1.15 0.356 0.204 1.65 0.55 0.304 10.92 9.75 0.313 0.100 0.300 0.300 0.260 0.200 0.150 0.060 TYP. 3.32 0.020 0.045 0.014 0.008 0.065 0.022 0.012 0.430 0.384 MAX. MIN. TYP. 0.131 MAX. inch
OUTLINE AND MECHANICAL DATA
DIP-8
13/17
Package mechanical data Figure 16. SO-8 mechanical data and package dimensions
mm DIM. MIN. A A1 A2 b c D
(1)
L6384E
inch MAX. 1.750 MIN. TYP. MAX. 0.0689 0.0098
TYP.
OUTLINE AND MECHANICAL DATA
0.100 1.250 0.280 0.170 4.800 5.800 3.800 4.900 6.000 3.900 1.270 0.250 0.400 1.040 0
0.250 0.0039 0.0492 0.480 0.0110 0.230 0.0067
0.0189 0.0091
5.000 0.1890 0.1929 0.1969 6.200 0.2283 0.2362 0.2441 4.000 0.1496 0.1535 0.1575 0.0500 0.500 0.0098 1.270 0.0157 0.0409 8 0.100 0 8 0.0039 0.0197 0.0500
E E1(2) e h L L1 k ccc
Notes: 1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm in total (both side). 2. Dimension "E1" does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side.
SO-8
0016023 D
14/17
L6384E
Order codes
7
Order codes
Table 7. Order codes
Part number L6384E L6384ED L6384ED013TR Package DIP-8 SO-8 SO-8 Packaging Tube Tube Tape and reel
15/17
Revision history
L6384E
8
Revision history
Table 8.
Date 12-Oct-2007
Document revision history
Revision 1 First release Changes
16/17
L6384E
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